Future of F@H: folding speed and protein size

[Jonazz]

It's exciting to see how far we've come. One way to think about it is in terms of how long of a time scale and length scale we can simulate for protein folding and protein misfolding diseases (such as Aß aggregation in Alzheimer's Disease):

Time scales: advancing roughly 1000x every 5 years

2000: 1 to 10ns (Fs peptide)
2005: 1 to 10µs (villin, Aß aggregation of 4 chains)
2010: 1 to 10ms (NTL9, Lambda repressor)
2015: 1 to 10s?

Just breaking past a microsecond was a big deal. The fact that we can simulate 10's of milliseconds is very exciting, but I'm really excited about where this appears to be leading, allowing us to tackle really challenging and important problems. It would also mean that through a combination of new methods, algorithms, and hardware advances, we've already increased our capabilities by a million fold in just 10 years (2000 to 2010). We're looking forward to hopefully making it a billion fold in 2015!


Length scales: advancing roughly 2x every 5 years

2000: 16 amino acids (Fs)
2005: 35 amino acids (villin)
2010: 80 amino acids (lambda, ACBP)
2015: 160 amino acids?

It's also important to note that these are sizes for protein folding. For other problems, such as protein conformational change, we've already tackled much bigger systems.

I'm really excited to see what the next 5 years will bring!

This is from the folding blog. For comparison:

Abeta: 36–43 amino acids (protein involved with Alzheimers)
Immunoglobin: 70-110 amino acids (our body's antibodies)
Alpha-synuclein: 140 amino acids (most common size of the protein, linked to Parkinson's disease)
P53: 393 amino acids (prevents cancer, also called the 'protein suppressor')
Huntingtin: 3144 amino acids (You guessed it, linked to Huntington's disease)
Titin: 34,350 amino acids (largest protein, name refers to 'titan')

I couldn't find anything about the folding time scale of proteins, but I do know several proteins can take seconds to fold. Maybe someone can help me here?

FAH is well on its way to able to simulate proteins like P53 and Alpha-synuclein. Others, like Huntingtin, still seem a while away (which doesn't mean they aren't doin any Huntington research). Which proteins is the PG planning to tacke in the next few years? P53?

Folding@Home is really advancing rapidly, I can't wait to hear more

[gwildperson]

Hardware has improved rapidly. but the 10n, 10µs 10ms, 10s(?) scale is phenomenal. I wonder what part of that isn't just hardware. (Better software, more people doing FAH, etc.)

[Ivoshiee]

Hardware has improved rapidly. but the 10n, 10µs 10ms, 10s(?) scale is phenomenal. I wonder what part of that isn't just hardware. (Better software, more people doing FAH, etc.)

I wonder that as well, but I expect most power is coming from the software advances, because hardware is still getting better more or less linearly and there aren't so much boxes running FAH to push that slope very deep.

[Stonecold]

Hardware has improved rapidly. but the 10n, 10µs 10ms, 10s(?) scale is phenomenal. I wonder what part of that isn't just hardware. (Better software, more people doing FAH, etc.)

I wonder that as well, but I expect most power is coming from the software advances, because hardware is still getting better more or less linearly and there aren't so much boxes running FAH to push that slope very deep.

Linearly? But what about Moore's law? I thought that was suppose to apply for over 50 more years.

[Jesse_V]

Hardware has improved rapidly. but the 10n, 10µs 10ms, 10s(?) scale is phenomenal. I wonder what part of that isn't just hardware. (Better software, more people doing FAH, etc.)

I wonder that as well, but I expect most power is coming from the software advances, because hardware is still getting better more or less linearly and there aren't so much boxes running FAH to push that slope very deep.

Linearly? But what about Moore's law? I thought that was suppose to apply for over 50 more years.

Just because the transistor count in CPUs doubles every 1.5 years doesn't mean that the speed also doubles. Check out http://folding.typepad.com/news/2008/06 ... re-do.html and http://folding.typepad.com/news/2007/09 ... rks-f.html

[bruce]

linearly? But what about Moore's law? I thought that was suppose to apply for over 50 more years.

Just because the transistor count in CPUs doubles every 1.5 years doesn't mean that the speed also doubles. Check out http://folding.typepad.com/news/2008/06 ... re-do.html and http://folding.typepad.com/news/2007/09 ... rks-f.html

Moore's law isn't "linearly" it's exponential:
Both 1 2 4 8 16 32 64 ... (Moore's law) and the progression 10n, 10µs 10ms, 10s are exponential, though different factors over different timespans.

At the present time, doubling the number of transistors, in macroscopic terms, means doubling the number of CPUs on a chip. If you're running the SMP client, that does mean (almost) doubling the speed at which you fold. I'm not so sure what is happening to GPUs over the same time 1.5 year intervals.

The chart shows the number of FAH clients is increasing more or less linearly and that should be added to whatever you get from Moore's law for CPUs and some factor to what you get for GPUs.

[Alan C. Lawhon]

I read a recent interview with Gordon Moore in Fortune magazine. He was asked specifically how much longer he expects "Moores Law" to continue holding up? He said, (and I'm paraphrasing slightly), the ability to continue doubling the number of transistors was becoming more and more of a challenge as technology was beginning to bump up against certain physical limits. However, he also mentioned that engineers working on this "are doing incredible things at the atomic level," so he thought Moores Law "... might hold up a bit longer."

Concerning the Alpha synuclein protein, I hope going after that protein turns from a "proposed project" (or an experimental project) into an actual "crunching work units" project ASAP. My sister has Parkinson's and it makes me sick to see what she is going through. This is why I'm coming up with all these ideas (over in the General Discussion forum) for bringing in new donors. If Vijay needs another 100,000 CPUs and 100 TFLOPs of processing power to go after Alpha synuclein, then we're going to get him those 100,000 CPUs. I've been "spreading the word" among a number of folks I know in the past few days. It's hard to quantify as I don't know exact numbers, but there's a real possibility that somewhere between ten to thirty new folders are either coming onboard right now - or soon will be. By the time I'm done, I hope to get that number up into the thousands.

[bruce]

When Moore's Law was first proposed, the same thing was said: We're bumping up against a technological / physical limits and it can't continue for very long. Nobody in their right mind could have guessed that it could possibly continue to be true for for as long as it has. Nevertheless, somebody seems to always come along and create a better technology that happens to move the "for a bit longer" out another few years before we reach whatever the earlier limit was based on.

[Stonecold]

Moore's law isn't "linearly" it's exponential:
Both 1 2 4 8 16 32 64 ... (Moore's law) and the progression 10n, 10µs 10ms, 10s are exponential, though different factors over different timespans.

Yeah I know, I was saying that because Ivoshiee said "hardware is still getting better more or less linearly".

[stevedking]

Improved algorithms is what is needed.

[Frontiers]

Improved algorithms is what is needed.

Yep, exactly.

1. According to http://www.realworldtech.com/haswell-cpu/ new Intel's Haswell will have 4× boost in the peak FLOPs compared to Nehalem cores. I don't tnink that totally new Intel's architecture will arrive until 2016 and new AMD's architecture will arive until 2014.
2. Gromacs 4.6 have some amazing features like support of SSE4.1, AVX-128-FMA, AVX-256, multi-level hybrid parallelization & native GPU acceleration using CUDA.
3. It's very possibly that next generatons CPU's will not exceed stock 4 GHz clocks ever due to the physical/power limitations - http://ww.realworldtech.com/intel-22nm-finfet/2/ - 22nm Intel's Finfets operates at near 0.85 Volts, physical treshold for transistors is near 0.2-0.3 Volts, after few shrinks new desktop CPUs probably will operate at about twice above this treshold voltages.
4. It's very possible that next shrinks of Xeon Phi at HPC loads will outperform everything in term of GFLOPS/Watt computational efficiency - http://www.realworldtech.com/near-threshold-voltage/4/. Now Xeon Phi outperform 2 x 6 Core Xeons server boards at about 2.5 times at MD HPC loads with nearly same of even slightly lower power draw. This gap may be wider in the future due to Xeon Phi designs with more cores at lower voltages.

After rewriting MD tasks for Xeon Phi architecture F@H will have some risks to look not very power-efficient compared to industrial HPC superclasters, even with their additional power draws for high speed interboard interconnects, CPU interconnects, air conditioning or agressive CPU cooling to ambient T's in some designs.

It all looks like F@H will need in near future completely new hybrid core for both CPU/GPU simultaneous work, based on GROMACS 4.6 or higher, optimized for new CPU's with AVX/Haswell AVX, or even 2 fully optimized versions for Haswell/Broadwell and Piledriver/Steamroller cores.

The only way to compete with industrial Xeon Phi sucessors HPC clusters in terms of power-efficiency and cost of running is simultaneous downclocking&undervolting of mass-market high-end GPU's, or even running of 2-3 such GPU's in one host, therefore, GPU part of such future hybrid core should have maximum scalability in shaders amount domain, not in frequency domain.

[Frontiers]

Yeah I know, I was saying that because Ivoshiee said "hardware is still getting better more or less linearly".

But I suspect that unseen efforts of design/fab/equipment/management teams grows exponentially for hardware getting better linearly.

[mmonnin]

I do happen to know that the NAND cell has 3-4 generations left which includes EUV and DRAM has that and another generation as it is a bit behind in cell size. At that point we're basically counting atoms. NAND/DRAM are a bit different than CPU logic but a good part of a CPU die size shrink are the cache cells. At that point semiconductors will need some type of replacement from one of the many possible technologies that are out there hoping to be the next transistor gate.

[art_l_j_PlanetAMD64]

I do happen to know that the NAND cell has 3-4 generations left which includes EUV and DRAM has that and another generation as it is a bit behind in cell size. At that point we're basically counting atoms. NAND/DRAM are a bit different than CPU logic but a good part of a CPU die size shrink are the cache cells. At that point semiconductors will need some type of replacement from one of the many possible technologies that are out there hoping to be the next transistor gate.

I have heard reports that there are some experiments in going to deep 3D in semiconductor fabrication. That is, much more than the relatively shallow 3D that is being done currently.

In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.

[mmonnin]

Currently there are many products that stack chips on top of each other and the data paths are connected outside the chip. The next advancement is called TSV, through silicon via, where the connection is made with conductive paths chip to chip. (IN Lehman terms...Stack some chips, drill through all of them and fill it with a conductive material so they can all communicate). Think of Micron's Hybrid Memory Cube for this: http://hybridmemorycube.org/technology.html Another version would be adding multiple layers of transistors to a single die (process the chip once then repeat). The last 2 versions will reduce the % of the die that belongs to active cells as some more logic will be needed to route the extra connections. Which one is less and which one is less complicated may help determine which typewill be made. But none of these will reduce costs of a chip like a process shrink and some of these are only meant to reduce package size/increase speed.